¸ÚλְÔð£º
1.¸ºÔð¹«Ë¾ÈíÓ²Ò»Ì廯ÖÐоƬѡÐͲ¼¾Ö¡¢ÕûÌåÆÀ¹ÀºÍ¹æ»®¡£»ùÓÚºèÃÉÌØÐԺ͹«Ë¾Ñз¢ÐèÇó£¬Ñ¡ÔñºÍ¹æ»®ºÏÊʵÄSOCоƬƽ̨ºÍÑݽøÂ·Ïߣ»
2.¸ºÔðоƬÁìÓòµÄ¼¼ÊõÑݽøÂ·±ê¡¢³ÖÐø¸ú×ÙÐÐÒµ¼¼Êõ·¢Õ¹Ç÷ÊÆ£¬ÌáÈ¡ÓмÛÖµµÄºËÐļ¼Êõµã¼°¼¼Êõ·½Ïò£»
3.¸ºÔðÈí×ÜÏßASICоƬµÄÆÀ¹ÀºÍÕûÌåÉè¼Æ£¬°üÀ¨¼Ü¹¹Éè¼Æ¡¢¹¤ÒÕÆÀ¹À¡¢IPÑ¡Ôñ¡¢Ä£Ðͽ¨Á¢¡¢ÏµÍ³ÐÔÄÜÆÀ¹ÀµÈ£»
4.Ñз¢Á÷³Ì¸÷½×¶ÎÏà¹ØÎĵµµÄ׫д¡£
ÈÎÖ°ÒªÇó£º
1.Ñо¿ÉúÒÔÉÏѧÀú£¬¼¯³Éµç·¡¢Î¢µç×Ó¡¢Í¨Ðʤ³Ì¡¢µç×Ó¹¤³ÌÏà¹Ø×¨Òµ¡£²©Ê¿ÓÅÏÈ£»
2.ÊìϤarm¡¢RISC-VµÈϵÁд¦ÀíÆ÷SOC¼Ü¹¹£¬ÊìϤAXI¡¢AHB¡¢AMB¡¢AMBAµÈ×ÜÏ߼ܹ¹£¬ÊìϤоƬÁ÷Ë®Ïß¡¢Ê±Ðò¡¢¹¦ºÄºÍÐÔÄÜ·ÖÎö£¬ÊìϤ×ÜÏß¡¢¼ÓÃÜÒÔ¼°¸÷ÖÖ±ê×¼ÍâÉè½Ó¿Ú£»
3.ÊìϤVHDL/Verilog¡¢SVµÈÊý×ÖоƬÉè¼Æ¼°ÑéÖ¤ÓïÑÔ£¬²ÎÓë¹ýFPGAÉè¼Æ»òÑéÖ¤£»
4.ÊìϤоƬÉè¼Æ»ù±¾ÖªÊ¶£¬Èç´úÂë¹æ·¶¡¢¹¤×÷»·¾³ºÍ¹¤¾ß¡¢µäÐ͵ç·£¨Òì²½¡¢×´Ì¬»ú¡¢FIFO¡¢Ê±ÖÓ¸´Î»¡¢memory¡¢»º´æ¹ÜÀíµÈ£©£»
5.ÊìϤ³£ÓõÄÎÞÏßͨÐÅÐÒ飨802.11µÈ£©£¬Óж̾àͨÐÅÏà¹ØÁìÓòоƬµÄʵ¼ÊÁ÷Ƭ¾ÑéΪ¼Ñ¡£
6.Á¼ºÃµÄÖ°ÒµËØÑøºÍÍŶÓÐ×÷ÄÜÁ¦£¬Îĵµ¡¢¹µÍ¨¡¢Ñ§Ï°ÄÜÁ¦Ç¿¡£
ְλÀà±ð£º
ÆäËû
¾Ù±¨